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cmos dram K4Q153211M, k4q153212m this is a 524,288 x 32 bit extended data out cmos dram. extended data out mode offers high speed random access of memory cells within the same row, so called hyper page mode. power supply voltage (+5.0v or +3.3v), refresh cycle 1k, access time (-50 or -60 ), power consumption(normal or low power) and soj package type are optional features of this family. all of this family have cas -before- ras refresh, ras -only refresh and hidden refresh capabilities. furthermore, self-refresh operation is available in l-version. this 512kx32 edo mode quad cas dram is fabricated using samsung's advanced cmos process to realize high band-width, low power consumption and high reliability. ? part identification - K4Q153211M-jc (5.0v, 1k ref.) - K4Q153211M-jl (5.0v, 1k ref. lp) - k4q153212m-jc (3.3v, 1k ref.) - k4q153212m-jl (3.3v, 1k ref. lp) ? extended data out mode operation (fast page mode with extended data out) ? four separate cas pins provide for separate i/o operation ? cas -before- ras refresh capability ? ras -only and hidden refresh capability ? self-refresh capability (l-ver only) ? ttl(5v)/lvttl(3.3v) compatible inputs and outputs ? early write or output enable controlled write ? jedec standard pinout ? plastic soj 400mil x 1125mil package ? single +5.0v 0.5v power supply(5v product) ? single +3.3v 0.3v power supply(3.3v product) control clocks vbb generator refresh timer refresh control refresh counter row address buffer col. address buffer row decoder column decoder ras cas 0-3 w vcc vss dq0 to dq7 a0 - a9 a0 - a8 memory array 524,288 x 32 cells samsung electronics co., ltd. reserves the right to change products and specifications without notice. 512k x 32bit cmos quad cas dram with edo description features functional block diagram ? performance range speed t rac t cac t rc t hpc remark -50 50ns 15ns 84ns 20ns 5.0v only -60 60ns 17ns 104ns 27ns 5v/3.3v s e n s e a m p s & i / o cas 0 d/i buffer oe ? refresh cycles part no. v cc refresh cycle refresh period normal l-ver 153211m-j 5.0v 1k 16ms 128ms 153212m-j 3.3v 1k 16ms 128ms ? active power dissipation speed 3.3v 5.0v -50 - 880 -60 540 825 unit : mw cas 0 d/o buffer cas1 d/i buffer cas1 d/o buffer cas2 d/i buffer cas2 d/o buffer cas3 d/i buffer cas3 d/o buffer dq8 to dq15 dq16 to dq23 dq24 to dq31
cmos dram K4Q153211M, k4q153212m pin configuration (top views) pin name pin function a0 - a9 address inputs dq0 - 31 data in/out ras row address strobe cas 0 - 3 column address strobe w read/write input oe data output enable v ss ground v cc power(+5v) power(+3.3v) n.c no connection v cc dq0 dq1 dq2 dq3 v cc dq4 dq5 dq6 dq7 n.c v cc dq8 dq9 dq10 dq11 v cc dq12 dq13 dq14 dq15 n.c n.c n.c n.c n.c ras a0 a1 a2 a3 a4 a5 a6 v cc v ss dq31 dq30 dq29 dq28 v ss dq27 dq26 dq25 dq24 n.c v ss dq23 dq22 dq21 dq20 v ss dq19 dq18 dq17 dq16 n.c cas 0 cas 1 cas 2 cas 3 w oe n.c n.c n.c a9 a8 a7 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 * 24 25 26 27 28 29 30 31 32 33 34 35 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 k4q153211(2)m-j j : 400mil 70pin soj * pin23 : must be nc or v ss
cmos dram K4Q153211M, k4q153212m absolute maximum ratings * permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol rating units 3.3v 5v voltage on any pin relative to v ss v in, v out -0.5 to +4.6 -1.0 to +7.0 v voltage on v cc supply relative to v ss v cc -0.5 to +4.6 -1.0 to +7.0 v storage temperature tstg -55 to +150 -55 to +150 c power dissipation p d 1 1 w short circuit output current i os address 50 50 ma recommended operating conditions (voltage referenced to vss, t a = 0 to 70 c ) *1 : v cc +1.3v/15ns(3.3v), v cc +2.0v/15ns(5v), pulse width is measured at v cc *2 : -1.3v/15ns(3.3v), -2.0v/20ns(5v), pulse width is measured at v ss parameter symbol 3.3v 5v units min typ max min typ max supply voltage v cc 3.0 3.3 3.6 4.5 5.0 5.5 v ground v ss 0 0 0 0 0 0 v input high voltage v ih 2.2 - v cc +0.3 *1 2.4 - v cc +1.0 *1 v input low voltage v il -0.3 *2 - 0.8 -1.0 *2 - 0.8 v dc and operating characteristics (recommended operating conditions unless otherwise noted.) max parameter symbol min max units 3.3v input leakage current (any input 0 v in v in +0.3v, all other input pins not under test=0 volt) i i(l) -5 5 ua output leakage current (data out is disabled, 0v v out v cc ) i o(l) -5 5 ua output high voltage level(i oh =-2ma) v oh 2.4 - v output low voltage level(i ol =2ma) v ol - 0.4 v 5v input leakage current (any input 0 v in v in +0.5v, all other input pins not under test=0 volt) i i(l) -5 5 ua output leakage current (data out is disabled, 0v v out v cc ) i o(l) -5 5 ua output high voltage level(i oh =-5ma) v oh 2.4 - v output low voltage level(i ol =4.2ma) v ol - 0.4 v
cmos dram K4Q153211M, k4q153212m *note : i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 , i cc3 and i cc6, address can be changed maximum once while ras =v il . in i cc4 , address can be changed maximum once within one hyper page mode cycle time, t hpc . dc and operating characteristics (continued) i cc1 * : operating current ( ras and cas cycling @t rc =min. ) i cc2 : standby current ( ras = cas = w = v ih ) i cc3 * : ras -only refresh current ( cas = v ih , ras , address cycling @t rc =min. ) i cc4 * : hyper page mode current ( ras = v il , cas , address cycling @t hpc =min. ) i cc5 : standby current ( ras = cas = w = v cc -0.2v ) i cc6 * : cas -before- ras refresh current ( ras , cas cycling @t rc =min. ) i cc7 : battery back-up current, average power supply current, battery back-up mode input high voltage(v ih ) = v cc -0.2v, input low voltage(v il ) = 0.2v, cas = 0.2v, din = don't care, t rc = 125us(1k/l-ver) t ras = t ras min~300ns i ccs : self refresh current ras = cas 0~3 =v il , w = oe = a0 ~ a9 = v cc -0.2v or 0.2v, dq0 ~ dq31 = v cc -0.2v, 0.2v or open symbol power speed max units k4q153212m-j K4Q153211M-j i cc1 don't care -50 -60 - 150 160 150 ma ma i cc2 normal l-ver don't care - 1 2 1 ma ma i cc3 don't care -50 -60 - 150 160 150 ma ma i cc4 don't care -50 -60 - 100 110 100 ma ma i cc5 normal l-ver don't care 500 300 1000 500 ua ua i cc6 don't care -50 -60 - 150 160 150 ma ma i cc7 l-ver don't care 300 500 ua i ccs l-ver don't care 200 300 ua
cmos dram K4Q153211M, k4q153212m capacitance (t a =25 c , v cc =5v or 3.3v, f=1mhz) parameter symbol min max units input capacitance [a0 ~ a9] c in1 - 5 pf input capacitance [ ras , cas x, w , oe ] c in2 - 7 pf output capacitance [dq0 - dq31] c dq - 7 pf test condition (3.3v device) : v cc =3.3v 0.3v, vih/vil=2.2/0.8v, voh/vol=2.0/0.8v note) *1 : 5v only parameter symbol -50 *1 -60 units notes min max min max random read or write cycle time t rc 84 104 ns read-modify-write cycle time t rwc 115 140 ns access time from ras t rac 50 60 ns 3,4,10 access time from cas t cac 15 17 ns 3,4,5,18 access time from column address t aa 25 30 ns 3,10 cas to output in low-z t clz 3 3 ns 3,18 output buffer turn-off delay from cas t cez 3 13 3 15 ns 6,11,18 oe to output in low-z t olz 3 3 ns 3 transition time (rise and fall) t t 2 50 2 50 ns 2 ras precharge time t rp 30 40 ns ras pulse width t ras 50 10k 60 10k ns ras hold time t rsh 13 17 ns 14 cas hold time t csh 40 48 ns 17 cas pulse width t cas 8 10k 12 10k ns 23 ras to cas delay time t rcd 20 35 20 43 ns 4,16 ras to column address delay time t rad 15 25 15 30 ns 10 cas to ras precharge time t crp 5 5 ns 15 row address set-up time t asr 0 0 ns row address hold time t rah 10 10 ns column address set-up time t asc 0 0 ns 16 column address hold time t cah 8 10 ns 16 column address to ras lead time t ral 25 30 ns read command set-up time t rcs 0 0 ns read command hold time referenced to cas t rch 0 0 ns 8,15 read command hold time referenced to ras t rrh 0 0 ns 8 write command hold time t wch 10 10 ns 14 write command pulse width t wp 10 10 ns write command to ras lead time t rwl 13 15 ns write command to cas lead time t cwl 8 10 ns 17 ac characteristics (0 c t a 70 c , see note 1,2) test condition (5v device) : v cc =5.0v 0.5v, vih/vil=2.4/0.8v, voh/vol=2.0/0.8v
cmos dram K4Q153211M, k4q153212m ac characteristics (continued) note) *1 : 5v only parameter symbol -50 *1 -60 units notes min max min max data set-up time t ds 0 0 ns 9 data hold time t dh 8 10 ns 9 refresh period (1k, normal) t ref 16 16 ms refresh period (l-ver) t ref 128 128 ms write command set-up time t wcs 0 0 ns 7,16 cas to w delay time t cwd 32 36 ns 7,14 ras to w delay time t rwd 67 79 ns 7 column address w delay time t awd 42 49 ns 7 cas precharge to w delay time t cpwd 47 54 ns 7 cas set-up time ( cas -before- ras refresh) t csr 5 5 ns 16 cas hold time ( cas -before- ras refresh) t chr 10 10 ns 15 ras to cas precharge time t rpc 5 5 ns 16 access time from cas precharge t cpa 28 35 ns 3,15 hyper page mode cycle time t hpc 20 27 ns 12,19 hyper page read-modify-write cycle time t hprwc 47 56 ns 12,19 cas precharge time (hyper page cycle) t cp 7 7 ns 20 ras pulse width (hyper page cycle) t rasp 50 200k 60 200k ns ras hold time from cas precharge t rhcp 30 35 ns oe access time t oea 13 15 ns 21 oe to data delay t oed 13 15 ns 22 output buffer turn off delay time from oe t oez 3 13 3 15 ns 6 oe command hold time t oeh 13 15 ns output data hold time t doh 5 5 ns output buffer turn off delay from ras t rez 3 13 3 15 ns 6,11 output buffer turn off delay from w t wez 3 13 3 15 ns 6 w to data delay t wed 15 15 ns oe to cas hold time t och 5 5 ns cas hold time to oe t cho 5 5 ns oe precharge time t oep 5 5 ns w pulse width (hyper page cycle) t wpe 5 5 ns ras pulse width ( c -b- r self refresh) t rass 100 100 us 25,26,27 ras precharge time ( c -b- r self refresh) t rps 90 110 ns 25,26,27 cas hold time ( c -b- r self refresh) t chs -50 -50 ns 25,26,27 hold time cas low to cas high t clch 5 5 ns 13,24
cmos dram K4Q153211M, k4q153212m notes an initial pause of 200us is required after power-up followed by any 8 ras -only refresh or cas -before- ras refresh cycles before proper device operation is achieved. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih (min) and v il (max) and are assumed to be 2ns for all inputs. measured with a load equivalent to 1 ttl load and 50pf. operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . assumes that t rcd 3 t rcd (max). this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . t wcs , t rwd , t cwd , t awd and t cpwd are non restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. if t cwd 3 t cwd (min), t rwd 3 t rwd (min), t awd 3 t awd (min) and t cpwd 3 t cpwd (min), then the cycle is a read- modify-write cycle and the data output will contain the data read from the selected address. if neither of the above conditions is satisfied, the condition of the data out is indeterminate. either t rch or t rrh must be satisfied for a read cycle. these parameters are referenced to the first cas falling edge in early write cycles and to w falling edge in oe controlled write cycle and read-modify-write cycles. operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as a reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled by t aa . if ras goes high before cas high going, the open circuit condition of the output is achieved by cas high going. if cas goes high before ras high going, the open circuit condition of the output is achieved by ras high going. t asc 3 6ns, assume t t = 2.0ns. in order to hold the address latched by the first cas going low, the parameter t clch must be met. the last cas x edge to go low. the last cas x edge to go high. the first cas x edge to go low. the first cas x edge to go high. output parameter is refrenced to corresponding cas x input. the last rising cas x edge to next cycle s last rising cas x edge. the last rising cas x edge to first falling cas x edge. the first dqx controlled by the first cas x to go low. the last dqx controlled by the last cas x to go high. each cas x must meet minimum pulse width. the last falling cas x edge to the first rising cas x edge. if t rass 3 100us, then ras precharge time must use t rps instead of t rp . for ras -only refresh and burst cas -before- ras refresh mode, 1024(1k) cycles of burst refresh must be executed within 16ms before and after self refresh, in order to meet refresh specification. for distributed cas -before- ras with 15.6us interval, cas -before- ras refresh should be executed with in 15.6us immedi- ately before and after self refresh in order to meet refresh specification. 6. 5. 9. 8. 3. 2. 1. 4. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 10. 11. 12. 24. 25. 26. 7. 27.
cmos dram K4Q153211M, k4q153212m t crp ras v ih - v il - cas0 v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq31 2 words read cycle column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t aa t oea t cac t clz t rac open t rrh t rch don't care undefined t rcs cas1 v ih - v il - t crp cas2 v ih - v il - t crp cas3 v ih - v il - t clch t rez t oez t cez t wez data-out t olz t roh t crp
cmos dram K4Q153211M, k4q153212m byte wide read cycle ras v ih - v il - cas0 v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t aa t oea t cac t clz t rac open t rrh t rch don't care undefined t rcs cas1 v ih - v il - cas2 v ih - v il - cas3 v ih - v il - note : d out = open t oez data-out t olz t roh t clch open open t wez data-out open v ih - v il - dq0~7 v ih - v il - v ih - v il - v ih - v il - dq8~15 dq16~23 dq24~31 t cez t rez t aa t oea t cac t rac t clz t olz t wez t rez t cez t crp t crp t crp t crp
cmos dram K4Q153211M, k4q153212m t wcs 2 words write cycle ( early write ) note : d out = open a v ih - v il - w v ih - v il - oe v ih - v il - row address t ral t rad t asr t rah t asc t ds t dh t wch don't care data-in undefined t crp ras v ih - v il - cas0 v ih - v il - t ras t rc t crp t rp t csh t rsh t rcd t cas t crp cas1 v ih - v il - t crp cas2 v ih - v il - t crp cas3 v ih - v il - t clch v ih - v il - dq0 ~ dq31 column address t cah t wp
cmos dram K4Q153211M, k4q153212m t wcs byte wide write cycle ( early write ) note : d out = open a v ih - v il - w v ih - v il - oe v ih - v il - row address t ral t rad t asr t rah t asc t cah t wp t wch t cwl t rwl don't care undefined t crp ras v ih - v il - cas0 v ih - v il - t ras t rc t crp t rp t csh t rsh t rcd t cas cas1 v ih - v il - t crp cas2 v ih - v il - cas3 v ih - v il - column address t csh v ih - v il - dq0~7 v ih - v il - v ih - v il - v ih - v il - dq8~15 dq16~23 dq24~31 t ds t ds t dh data-in t clch t dh t crp t crp data-in
cmos dram K4Q153211M, k4q153212m t oed a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq31 column address row address t ral t rad t asr t rah t asc t cah data-in t wp don't care 2 words write cycle ( oe controlled write ) note : d out = open t cwl t rwl t ds t dh t oeh undefined t crp ras v ih - v il - cas0 v ih - v il - t ras t rc t crp t rp t csh t rsh t rcd t cas t crp cas1 v ih - v il - t crp cas2 v ih - v il - t crp cas3 v ih - v il - t clch
cmos dram K4Q153211M, k4q153212m w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq31 valid t wp don't care 2 words read - modify - write cycle t rwl t cwl t oez t oed t awd t cwd data-out undefined valid data-in t rac t aa t ds t dh a v ih - v il - row address t ral t rad t asr t rah t asc t cah t oea t rwd t olz t crp ras v ih - v il - cas0 v ih - v il - t ras t rc t crp t rp t csh t rsh t rcd t cas t crp cas1 v ih - v il - t crp cas2 v ih - v il - t crp cas3 v ih - v il - t clch column address t cac t clz
cmos dram K4Q153211M, k4q153212m t rch t oez t clz ras v ih - v il - v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0~7 column address row addr t rhcp t rasp t cas t asc t rad t asr t rah t crp valid don't care hyper page mode read cycle t oez t rrh data-out undefined valid data-out column address column address t rsh t cas t rcd t hpc ? t cah ? ? ? t rch ? t rcs t rcs t rcs t oea t clz t aa t oez t rac t aa ? ? t cp t cas t rp t cp v ih - v il - v ih - v il - v ih - v il - cas0 cas1 cas2 cas3 ? ? t clch t asc v ih - v il - v ih - v il - v ih - v il - t hpc t cpa t aa t cpa t cac ? t clz valid data-out valid data-out valid data-out valid data-out valid data-out ? valid data-out dq8~15 dq16~23 dq24~31 t clch t rch t olz t csh t asc t ral t rac t clz ? ? t cah t cah t asc
cmos dram K4Q153211M, k4q153212m t asc t cah ras v ih - v il - cas0 v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - column address row addr t rhcp t rasp t cas t rad t asr t rah t asc t crp valid don't care hyper page mode write cycle ( early write ) data-in undefined valid data-in t ds note : d out = open column address t rsh t cas t rcd t hpc ? t csh t cah ? ? ? t wcs t wch t wcs t wp t wp t wch t wcs t wch t dh t ds t dh t ds ? ? ? t rp t cp t cp t cas t hpc cas1 v ih - v il - t cas ? t cas cas2 v ih - v il - t cas ? t cas cas3 v ih - v il - t cas ? v ih - v il - valid data-in t ds valid data-in t dh t ds v ih - v il - valid data-in valid data-in t ds t dh t ds t dh v ih - v il - valid data-in t ds dq0~7 dq8~15 dq16~23 dq24~31 t dh t dh valid data-in t dh ? ? ? ? ? ? ? ? t wp column address t cah t asc t ral
cmos dram K4Q153211M, k4q153212m t cac t asc t asc ras v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq31 row addr t rasp t asr valid don't care 2 words hyper page read - modify - write cycle data-out undefined t rcd t cp t rad t cah t wp t dh col. addr col. addr t cas t cas t cah t ral t prwc t rcs t cwl t cwd t awd t rwd t wp t cwd t awd t aa t rac t oea t clz t cac t oez t oed valid data-in valid data-out valid data-in t clz t ds t oea t aa t dh t ds t oez t oed t rwl t rp t rsh t rah t clch t cas t cas t cas t cas cas0 v ih - v il - cas1 v ih - v il - cas2 v ih - v il - cas3 v ih - v il - t clch t cwl t csh t crp
cmos dram K4Q153211M, k4q153212m ras v ih - v il - casx v ih - v il - a v ih - v il - row addr t ras t rc t rp t asr t rah t crp don't care ras - only refresh cycle undefined note : w , oe , d in = don't care d out = open t rpc t crp cas - before - ras refresh cycle note : w , oe , a = don't care ras v ih - v il - casx v ih - v il - t ras t rc t rp t rpc t rp t cp t chr t csr t cez t rpc v ih - v il - dq0 ~ dq31 open
cmos dram K4Q153211M, k4q153212m t cez ras v ih - v il - casx v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dqx hidden refresh cycle ( read ) column address row address t ras t rc t chr t rcd t rad t asr t rah t asc t cah t crp t rcs t aa t oea t cac t clz t rac open don't care t rsh t oez undefined t rc data-out t rp t rp t ras t wrh t ral
cmos dram K4Q153211M, k4q153212m ras v ih - v il - casx v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - hidden refresh cycle ( write ) column address row address t ras t rc t chr t rcd t rad t asr t rah t asc t cah t crp don't care t rsh data-in undefined t rc note : d out = open t wch t wp t dh t rp t rp t ras t ds t wcs dqx t ral
cmos dram K4Q153211M, k4q153212m don't care undefined cas - before - ras self refresh cycle note : oe , a = don't care ras v ih - v il - casx v ih - v il - t rass t rps t rpc t chs t rp t cp t csr t cez t rpc open v oh - v ol - dqx
cmos dram K4Q153211M, k4q153212m 0 . 4 0 5 ( 1 0 . 2 9 ) 0 . 4 3 5 ( 1 1 . 0 5 ) 1.130(28.70) 1.142(29.01) 0 . 1 4 2 ( 3 . 6 1 ) 0.020(0.51) 0.010(0.25) 0.027 (0.69) 0.012(0.30) 0 . 3 7 5 ( 9 . 5 3 ) min #70 0.030(0.76) 0.0315(0.8) units : inches (millimeters) package dimensions #36 #1 #35 0.004(0.1) 0 . 4 4 5 ( 1 1 . 3 0 ) 0 . 3 9 5 ( 1 0 . 0 3 ) 0 . 3 6 5 ( 9 . 2 7 ) 0.008(0.20) 0 . 1 3 2 ( 3 . 3 5 ) 0.017(0.43) 0.015(0.40) typ 0.025(0.64) 400mil 70-pin soj max 1.120(28.45)

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